1. Industrial Field
The present invention relates to a liquid crystal display and to an integrated circuit having a multi-port data output section.
The invention relates also to a driving method and a driver of liquid crystal display such as active matrix drive system and, more particularly, the reduction of EMI in a TFT liquid crystal display (hereinafter referred to as TFT-LCD panel).
The invention relates further to a liquid crystal display and, more particularly, to delivery of signal between a dedicated IC for driving the liquid crystal display and a source driver IC.
2. Prior Arts
1) Generally, a system in which frequency of data output signals is lowered and total number of the data output signals is increased with respect to data input signals, is called multi-port output. For example, when a frequency of data output signals is half of that of a data input signal and total number of the data output signals is twice as many as that of the data input signals, it is called two-port output.
In the arrangement of an electric circuit of a liquid crystal display, when an integrated circuit for generating display data output signals of two-ports is required, an internal clock signal used as a clock signal of a latch circuit located immediately before the display data output section in the integrated circuit is usually generated through a divider circuit for dividing into two frequencies to which a clock input signal is inputted, lowering a frequency thereof to be a half of the frequency of the clock input signals.
In the output section, the clock output signal is generated with the same phase as the point of changing the internal clock signal, and the display data output signals are generated so as to change with a time lag by a half frequency of the clock output signal (by a period “H” or a period “L”) from an active edge of the clock output signal serving as an edge for latching in the source driver IC.
This means that the display data output signals are generated so as to change simultaneously at the same point as the active edge of one type of internal clock signal which is an edge for latching the data with the internal clock signal in the circuit.
FIG. 22 shows diagrams respectively illustrating, in the form of voltage waveform, a relation between the input and output signal sections in the above-mentioned conventional integrated circuit for generating the mentioned two port-display data output signals. In the diagrams, reference numeral 1 indicates a clock input signal, numeral 2 indicates a display data input signal, numeral 3 indicates an internal clock signal, numeral 4 indicates a clock output signal, and numeral 5 indicates a display data output signal. Period of the display data input signal 2 is equal to the period 1CLKI of the clock input signal 1, and period of the display data output signal 5 is equal to the period 1CLK of the internal clock signal 3 and to the period 1CLKO of the clock output signal 4. 1CLK is a duration equivalent to 2CLKI, and 1CLKO is a duration equivalent to 2CLKI. Arrows of the internal clock signal 3 indicate active edges (trailing edge in the diagram) of the latch circuit located immediately before the display data output section in the integrated circuit, and arrows of the clock output signal 4 indicate active edges (leading edge in the diagram) of the latch circuit located immediately after the display data input section in the source driver IC to which the display data output signal 5 is outputted.
In the arrangement of electric circuit for any other system than the liquid crystal display, when an integrated circuit for generating a data output signal of multi-port having two ports or more with respect to the data input signal is required, usually, the internal clock signal in the integrated circuit is generated in the same manner as the foregoing through a divider circuit such that frequency thereof is an inverse number of a value obtained by multiplying the number of output ports by an integer.
In the output section, the data output signal is generated so as to change simultaneously at the same point as the active edge of the internal clock signal which is an edge for latching the data with a type of internal clock signal in the circuit.
FIG. 23 shows diagrams respectively illustrating, in the form of voltage waveform, a relation between the input and output signal sections in the above-mentioned conventional integrated circuit for generating a data output signal of multiple ports (n ports: n is an optional integer) having two ports or more. In the diagrams, reference numeral 1 indicates a clock input signal, numeral 3 indicates an internal clock signal, numeral 4 indicates a clock output signal, numeral 6 indicates a data input signal, and numeral 7 indicates a data output signal. Period of the data input signal 6 is equal to the period 1CLKI of the clock input signal 1, and period of the data output signal 7 is equal to the period 1CLK of the internal clock signal 3 and to the period 1CLKO of the clock output signal 4. 1CLK is a duration equivalent to nCLKI, and 1CLKO is a duration equivalent to nCLKI. Arrows of the internal clock signal 3 indicate active edges (trailing edge in the diagram) of the latch circuit located immediately before the data output section in the integrated circuit, and arrows of the clock output signal 4 indicate active edges (leading edge in the diagram) of the latch circuit located immediately after the data input section in the circuit to which the data output signal is outputted. However, the clock input signal 1 and the clock output signal 4 are not always set in the form of input and output terminals.
2) FIG. 24 is a simple block diagram of a driver circuit for a TFT-LCD panel, and in which reference numeral 218 indicates a TFT-LCD panel, numeral 215 indicates a TFT source line driver circuit (hereinafter referred to as source driver) for displaying the TFT-LCD panel, numeral 217 indicates a TFT gate line driver circuit (hereinafter referred to as gate driver) for displaying the TFT-LCD panel, numeral 211 indicates a display timing control circuit (hereinafter referred to as LCD timing controller) for generating various data and timing signals necessary for display operation and outputting them to the source driver 215 and to the gate driver 217, numeral 212 indicates a data bus for transferring, for example, a red display data (hereinafter referred to as R data) from the LCD timing controller to the source driver 215, numeral 213 is a data bus for transferring, for example, a green data (hereinafter referred to as G data), and numeral 214 is a data bus for transferring, for example, a blue data (hereinafter referred to as B data). Numeral 216 indicates a transfer clock signal line for transferring the display data of R, G, B from the LCD timing controller 211 to the source driver 215.
Detailed description of the entire operation of the arrangement shown in FIG. 24 is herein omitted, and the operation according to the invention is briefly described below. Referring to FIG. 24, in case of SVGA, for example, in the TFT-LCD panel 218, there exist 600 lines (trains) in each of which 800 picture elements composed of red, green and blue liquid crystal cells are arranged in a row.
The source driver IC 215 takes, synchronously with the clock for data transfer, the display data of the 800 picture elements sent by each data bus 212, 213, 214 of R, G, B from the LCD timing controller 211, and outputs the display data to the picture element lines of the TFT-LCD panel 218 after converting them to a voltage. At this time, the voltage outputted from the source driver IC 215 is taken into one picture element line specified from among the 600 lines by the gate driver IC 217. This operation is performed 600 times to complete the display of one picture of panel. Generally, rewriting operation of the picture is performed 60 times per second.
FIG. 25 is a diagram showing timing waveforms of the data bus when each data of R, G, B is transferred from the LCD timing controller 211 to the TFT source driver in FIG. 24.
In this example, to reproduce 64 gradations for each color R, G, B, each of the RGB data is formed by a data bus of 6 bits.
Generally, to change the data on these RGB data buses, all buses are changed simultaneously with the transfer clock 216. Since the source driver IC 215 takes the data synchronously with the transfer clock 216 (leading edge of the transfer clock 216 in this example), to make easy the timing control (to secure data setup and data hold timing), all data are changed at the edge reverse to the edge of the transfer clock where the data are taken by the source driver IC 215 (at the trailing edge in this example), as shown in FIG. 25.
Generally in the SVGA panel, frequency of the transfer clock is so high as to be about 40 MHz, and the RGB data, each being 6 bits and 18 bits in total, are changed in a short period of about 25 nS depending on the contents thereof.
The RGB display data output circuit of the LCD timing controller IC 211, the RGB data buses, and the source driver IC 215 connected to the output circuit of the LCD timing controller IC 211 respectively shown in FIG. 24 can be shown in the form of a simple equivalent circuit as shown in FIG. 26.
In this equivalent circuit, the RGB data buses and the source driver IC are shown as capacity load. That is, in FIG. 26, reference numeral 204 indicates a load capacity obtained by aggregating a wiring capacity of the R data bus 212 and an input capacity of the plural source driver ICs 215 connected to the R data bus, numeral 205 indicates a load capacity obtained by aggregating a wiring capacity of the G data bus 213 and an input capacity of the plural source driver ICs 215 connected to the G data bus 213, and numeral 206 indicates a load capacity obtained by aggregating a wiring capacity of the B data bus 214 and an input capacity of the plural source driver ICs 215.
Among the output circuits for outputting the RGB data in the LCD timing controller IC 211, numeral 201 indicates an output circuit for outputting the R data, numeral 202 indicates an output circuit for outputting G data, and numeral 203 indicates an output circuit for outputting B data.
It is to be noted that, though the display data of RGB are respectively formed of 6 bits in this example, the data output circuits and capacity load are shown each by 1 bit of RGB in FIG. 26.
3) In most of the conventional liquid crystal displays, an output from the dedicated IC is either outputted to the source driver IC as it is or outputted by inverting the polarity when a half number of data are simultaneously changed.
FIG. 28 is a block diagram showing the delivery of signals between the dedicated IC and the source driver IC in the conventional liquid crystal display.
In the diagram, reference numeral 301 indicates an internal bus for transmitting data of 3011 to 301n bits. Numeral 302 indicates a selector to which data on the internal bas 301 is inputted, and in which selectors 3021 to 302n are provided corresponding to the internal bus 301 and each being composed of an exclusive OR circuit of two inputs.
Numeral 303 indicates a register of n bits composed of registers 3011 to 303n to which output of the selector section 302 is inputted. Numeral 304 indicates an output buffer section composed of output buffers 3041 to 304n corresponding to the register 303 and to which data of the register section 303 are inputted, and numeral 305 indicates an output pin composed of output pins 3051 to 305n corresponding to the output buffer 304 and from which data of the output buffer 304 are outputted to external buses.
Numeral 306 indicates a comparative majority circuit which compares the data of the internal bus 301 and outputs a judgment output signal J for setting the selector 302 to inversion mode. Numeral 307 indicates an exclusive OR circuit of the selector 302, numeral 308 indicates a toggle type flip-flop for outputting a polarity display signal P through an output buffer 309 and an output pin 310. Numeral 311 indicates a clock signal line through which a clock signal CK is transmitted, and numeral 312 indicates a reset signal line.
In the conventional signal delivery circuit of above arrangement, the selector 302 transmits the signal on the internal bus 301, with its polarity as it is or inverted, as an input to the register 303. The registers 3031 to 303n of n bits are initialized to “0” output state by the reset signal R and takes the input data synchronously with the clock signal CK given for each switching of the output from the clock signal line 311.
At this time, the comparative majority circuit 306 compares the input data for each bit corresponding to the data inputted for each switching of the output from the internal bus 301 of the register 303, and only when number of different data is larger than that of equal data, the judgment output signal J is changed to “1” level, and the selector 302 is set to the inversion mode. This judgment output signal J and the polarity display signal P from the toggle type flip-flop 308 are inputted to the exclusive OR circuit 307, and the output from the exclusive OR circuit 307 is inputted to the toggle type flip-flop 308. The toggle type flip-flop 308 is initialized by receiving the reset signal R, and the stage is inverted by receiving the clock signal CK when the output from the exclusive OR circuit 307 is “1”.
3. Problems to be Solved by the Invention
1) As described above, as a result of changing the data output signal of multi-ports having two ports or more only at one point where is the same point as the active edge of the internal clock signal, which is an edge for latching the data with the internal clock signal to one type of internal clock signal during one period of the internal clock signal, in other words, as a result of simultaneously changing every data output signal only at one point with respect to the time base, a momentary current generated from the output buffer at the time of changing the data output section is superposed at the same one point with respect to the time base and increased corresponding to number of output signals. Therefore, a problem exists in that electromagnetic wave noise in the input/output signal section and unnecessary electromagnetic interference (EMI) negatively affecting other system and circuit are enhanced.
The invention was made to solve the above-discussed problem and has an object of providing an integrated circuit having a liquid crystal display of high quality and amulti-port data output section and in which electromagnetic wave noise in the input/output signal section and unnecessary electromagnetic interference negatively affecting the other system or circuit are reduced.
2) FIG. 27 shows a voltage waveform of respective RGB data buses 212, 213, 214 when RGB data referring to FIG. 26 are transmitted.
In case of changing each RGB data to L, H, L synchronously with the trailing edge of the data transfer clock, when the data are changed from L to H, currents Ic1, Ic2, Ic3 for charging the load capacities 204, 205, 206 flow to each data bus, and when the data are changed from H to L, currents Id1, Id2, Id3 for discharging the load capacities flow to each data bus.
As these currents flow to a power source of IC 211 and to GND through the output circuit of the LCD timing controller IC 211, after all, a sum of these currents flows to the power source line inside and outside of the LCD timing controller IC 211 and to the GND line.
Accordingly, as shown in FIG. 27, in the simultaneous change of 18 bits in total of each RGB data bus, on condition that Ic1=Ic2=Ic3=Ic and Id1=Id2=Id3=Id, when the RGB data have changed from L to H, a large current 18 times as much as Ic comes to flow, and when the RGB data have changed from H to L, a large current 18 times as much as Id comes to flow to the power source line of the LCD timing controller IC and to the GND line.
In the charge and discharge of capacity load, particularly in the charge and discharge of a large current, a large change of electromagnetic field, i.e., an electromagnetic field noise occurs in and around the current path.
For example, it is estimated that the electromagnetic field noise occurring when all bits of the 18 bit data have been changed simultaneously at the clock period of 40 MHz reaches a fairly high level, and in fact there arises a problem such that a long time and a large amount of labor and cost must be spent to satisfy the standard on EMI in the TFT-LCD panel.
Accordingly, another object of the invention is to provide a data transfer method capable of reducing the mentioned electromagnetic field noise at the time of transferring display data from the LCD timing controller to the source driver IC in the TFT-LCD panel.
3) The delivery of data between the dedicated IC and the source driver IC is performed in the mentioned manner in the conventional liquid crystal display, and in which the data are inverted by the selectors only when polarity of more than half of n bits has been simultaneously changed.
For example, supposing 6 bit data most popularly used in the liquid crystal display, as red, green and blue have respectively 6 bits, total data number becomes 6×3 18, and therefore the inversion of data takes place when the majority of data (10 data or more) has been simultaneously changed.
Recently, the noise in the simultaneous change is a serious problem in view of preventing EMI. Such a conventional improvement is certainly effective when respective 6 bits of red, green and blue have been simultaneously changed, but the effect of changing only one data is shown even when 10 data have been changed.
In the conventional liquid crystal display, since the delivery of data between the dedicated IC and the source driver IC is performed in the mentioned manner, the simultaneous change of majority of data output signals is an essential condition for the inversion of data.
The invention was made to solve the above-discussed problem and has an object of providing a liquid crystal display capable of reducing number of simultaneous changes of data output signals by detecting a change between the data.
4. Means of Solution to the Problems
1) To accomplish the foregoing objects, there is provided according to the invention an integrated circuit in which multi-port data output signals are generated with respect to a data input signal, and points of changing said data output signals with respect to a time base are set with a time lag one another during one period of a reference internal clock signal, so that number of simultaneous changes of display data output signals is reduced.
It is preferable that, in the mentioned arrangement, the points of changing the data output signals with respect to the tame base are set to points respectively delayed from an active edge of the clock output signal by 0.5 period, 1 period, and 1.5 period of the data input signal.
It is preferable that the points of changing the data output signals with respect to the tame base are set to points respectively having a time lag one another from the active edge of the clock output signal by optional integer times as long as a half period of the data input signal.
It is preferable that the points of changing the data output signals with respect to the time base are set to points respectively having a time lag one another from the active edge of the clock output signal by optional integer times as long as a half period of the data input signal and by a delay time produced by a delay circuit added to the optional integer times as long as a half period of the data input signal.
There is also provided according to the invention an integrated circuit in which multi-port display data output signals are generated with respect to a data input signal, and points of changing said display data output signals with respect to a time base are set respectively having a time lag one another during one period of a clock output signal or a reference internal clock signal having a same phase as the clock output signal, so that number of simultaneous changes of display data output signals is reduced.
It is preferable that, in the mentioned arrangement, the points of changing the display data output signals with respect to the time base are set to points respectively delayed from an active edge of the clock output signal by 0.5 period, 1 period, and 1.5 period of the clock input signal or the display data input signal.
It is preferable that the points of changing the display data output signals with respect to the time base are set to points respectively having a time lag one another from the active edge of the clock output signal by optional integer times as long as a half period of the clock input signal or the display data input signal.
It is preferable that the points of changing the display data output signals with respect to the time base are set to points respectively having a time lag one another from the active edge of the clock output signal by optional integer times as long as a half period of the clock input signal or the display data input signal and by a delay time produced by a delay circuit added to the integer times as long as the half period of the clock input signal or the display data input signal.
2) There is provided according to the invention a driving method of a liquid crystal display in which when red, green and blue color display data composed of plural bits are transferred from a display timing circuit to a TFT drive circuit for driving a TFT liquid crystal panel to display, each transfer is performed with a time lag little by little for each bit unit formed of plural bits optionally selected from each of said color display data.
It is preferable that the bit unit is formed for each of red, green and blue color display data.
It is preferable that each bit unit has a part of the plural bits forming the red, green and blue color display data.
It is preferable that the bit unit is transferred with a time lag of 2 nanoseconds or longer.
A driver of a liquid crystal display according to the invention comprises: a TFT drive circuit for driving a TFT liquid crystal panel to display; a display timing control circuit for transferring red, green and blue color display data formed of plural bits to the TFT drive circuit for each bit unit formed of plural bits optionally selected from each of the color display data; and a delay unit provided in the display timing control circuit to delay the transfer timing between one bit unit and another.
3) A liquid crystal display according to the invention comprises: a data supply circuit for supplying image data through a signal line to a drive circuit for driving a display section; a detector circuit for detecting a coincidence of polarity by comparing a polarity of bit for each predetermined group of image data outputted by the data supply circuit; a first control circuit for outputting the data of the group represented by certain data to the signal line when the coincidence of polarity has been detected by the detector circuit; and a second control circuit for outputting the data of the group restored from the certain data of the signal line to the drive circuit when the coincidence of polarity of bit has been detected by the detector circuit.
It is preferable that the predetermined group of image data are red, green and blue data.
It is preferable that the certain data are red data.
It is preferable that the first control circuit controls the predetermined group of data to be a low potential, except the certain data.
It is also preferable that the second control circuit forms the predetermined group of data to be same as the certain data.
5. Advantages of the Invention
1) As a result of employing the arrangement described above according to the invention, it is now possible to provide an integrated circuit having a liquid crystal display of high quality and a data output section of multi-ports and in which electromagnetic wave noise in the input/output signal section and unnecessary electromagnetic interference negatively affecting the other system or circuit are reduced.
It is also possible that, as a result of reducing the simultaneous change of the data output signals by generating the multi-port data output signals and by setting the points of changing the display data output signals with respect to the tame base to plural two or three points respectively delayed by 0.5 period, 1 period, and 1.5 period of the clock input signal during one period of the clock output signal, amount of change at each point with respect to a momentary current generated from the entire output buffer at the time of changing the data output signals of the data output section is reduced, whereby electromagnetic wave noise in the input/output signal section and unnecessary electromagnetic interference (EMI) negatively affecting other system and circuit are reduced.
It is also possible that, as a result of reducing the simultaneous change of the data output signals by generating the multi-port data output signals and by setting the points of changing the display data output signals with respect to the tame base to plural points with a time lag one another by optional integer times as long as a half period of the clock input signal during one period of the reference internal clock signal, amount of change at each point with respect to a momentary current generated from the entire output buffer at the time of changing the data output signals of the data output section is reduced, whereby electromagnetic wave noise in the input/output signal section and unnecessary electromagnetic interference (EMI) negatively affecting other system and circuit are reduced.
It is also possible that, as a result of reducing the simultaneous change of the data output signals by generating the multi-port data output signals and by setting the points of changing the display data output signals with respect to the time base to plural points with a time lag one another by optional integer times as long as a half period of the clock input signal during one period of the reference internal clock signal and by a delay time produced by a delay circuit added to the integer times as long as the half period, amount of change at each point with respect to a momentary current generated from the entire output buffer at the time of changing the data output signals of the data output section is reduced, whereby electromagnetic wave noise in the input/output signal section and unnecessary electromagnetic interference (EMI) negatively affecting other system and circuit are reduced.
2) In the drive method of a liquid crystal display according to the invention, when the display data of RGB are transferred from the LCD timing controller IC to the source driver, since the points (timings) for changing RGB data buses respectively have a time lag little by little so as not to change the R data bus, G data bus and B data bus simultaneously, even if all of the RGB data bits are changed from L to H or from H to L, the current flowing at that time is dispersed, whereby electromagnetic field noise can be reduced.
Further, when the display data of RGB are transferred from the LCD timing controller IC to the source driver, since the bus width of the respective RGB data buses is divided from more significant bits by plural bit unit and the points (timings) of change respectively have a time lag between one divided data bit unit and another, even if all of the RGB data bits are changed from L to H or from H to L, the current flowing at that time is dispersed, whereby electromagnetic field noise can be reduced.
Furthermore, when the display data of RGB are transferred from the LCD timing controller IC to the source driver, since the optimum time lag amount in the points (timings) for changing the respective RGB data buses is set to 2 nanoseconds or longer, electromagnetic field noise can be reduced without occurring any trouble in the data sampling of the source driver IC.
3) The liquid crystal display of above arrangement can perform following advantages.
Since the liquid crystal display comprises a data supply circuit for supplying image data through a signal line to a drive circuit for driving a display section; a detector circuit for detecting a coincidence of polarity by comparing a polarity of bit for each predetermined group of image data outputted by the data supply circuit; a first control circuit for outputting the data of the group represented by certain data to the signal line when the coincidence of polarity has been detected by the detector circuit; and a second control circuit for outputting the data of the group restored from the certain data of the signal line to the drive circuit when the coincidence of polarity of bit has been detected by the detector circuit; the simultaneous change of polarity can be reduced.
Since a predetermined group of image data are red, green and blue data, the data can be processed by each picture element.
Since the certain data are red data, all of the data can be covered by ⅓ data for each picture element.
Since the first control circuit controls the predetermined group of data to be a low potential, except the certain data, change of polarity can be reduced.
Since the second control circuit forms the predetermined group of data to be same as the certain data, the data can be easily restored.